In conventional processes for the fabrication of CMOS integrated circuits which include both N channel FETs and P channel FETs, many masking steps are required. For example, the fabrication of sources and drains of FETs having lightly-doped drain extensions, sometimes referred to as reach-throughs, conventionally requires four masking steps. One masking step protects P channel FETs while a lightly-doped drain extension is implanted for N channel FETs. Another masking step protects N channel FETs while a lightly-doped drain extension is implanted for P channel FETs. Still another masking step protects P channel FETs while sources and drains are implanted for N channel FETs. Moreover, yet another masking step protects N channel FETs while sources and drains are implanted for P channel FETs.
It is desirable to minimize the number of masking steps needed to fabricate semiconductor devices. The removal of a masking step in a fabrication process improves device yield and directly reduces manufacturing costs. Consequently, a need exists for a process and a resulting structure which require fewer than four masking steps in the fabrication of sources and drains for N channel and P channel CMOS FETs.